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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 02 -- 13 June 2005 Product data sheet
1. General description
The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C754B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The SC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages.
2. Features
s 4 channel UART s 5 V, 3.3 V and 2.5 V operation s Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional enhancements, and software compatible with TL16C754 s Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s) s 5 V tolerant inputs s 64-byte transmit FIFO s 64-byte receive FIFO with error flags s Industrial temperature range (-40 C to +85 C) s Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation s Software (Xon/Xoff)/hardware (RTS/CTS) flow control x Programmable Xon/Xoff characters x Programmable auto-RTS and auto-CTS
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
s s s s s s s s
s s s s s s s
Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation Software selectable baud rate generator Prescaler provides additional divide-by-4 function Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics x 5, 6, 7, or 8-bit characters x Even, odd, or no-parity bit generation and detection x 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loop-back capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) Sleep mode
3. Ordering information
Table 1: Ordering information Package Name SC16C754BIBM SC16C754BIB80 SC16C754BIA68 LQFP64 LQFP80 PLCC68 Description plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm plastic leaded chip carrier; 68 leads Version SOT414-1 SOT315-1 SOT188-2 Type number
9397 750 14668
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Product data sheet
Rev. 02 -- 13 June 2005
2 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
4. Block diagram
SC16C754B
TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER
TXA to TXD
D0 to D7 IOR IOW RESET
DATA BUS AND CONTROL LOGIC
FLOW CONTROL LOGIC
INTERCONNECT BUS LINES AND CONTROL SIGNALS
RECEIVE FIFO REGISTERS
RECEIVE SHIFT REGISTER
RXA to RXD
A0 to A2 CSA to CSD
REGISTER SELECT LOGIC
FLOW CONTROL LOGIC
DTRA to DTRD RTSA to RTSD
INTA to INTD TXRDY RXRDY
INTERRUPT CONTROL LOGIC
CLOCK AND BAUD RATE GENERATOR
MODEM CONTROL LOGIC
CTSA to CTSD RIA to RID CDA to CDD DSRA to DSRD
INTSEL
002aaa866
XTAL1 XTAL2
CLKSEL
Fig 1. Block diagram of SC16C754B
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5. Pinning information
5.1 Pinning
61 GND 49 CDD 48 DSRD 47 CTSD 46 DTRD 45 GND 44 RTSD 43 INTD 42 CSD 41 TXD 40 IOR 39 TXC 38 CSC 37 INTC 36 RTSC 35 VCC 34 DTRC 33 CTSC DSRB 17 CDB 18 RIB 19 RXB 20 VCC 21 A2 22 A1 23 A0 24 XTAL1 25 XTAL2 26 RESET 27 GND 28 RXC 29 RIC 30 CDC 31 DSRC 32
002aab564
64 CDA
51 RXD
62 RXA
52 VCC
DSRA CTSA DTRA VCC RTSA INTA CSA TXA IOW
1 2 3 4 5 6 7 8 9
SC16C754BIBM
TXB 10 CSB 11 INTB 12 RTSB 13 GND 14 DTRB 15 CTSB 16
Fig 2. Pin configuration for LQFP64
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Product data sheet
Rev. 02 -- 13 June 2005
50 RID
63 RIA
60 D7
59 D6
58 D5
57 D4
56 D3
55 D2
54 D1
53 D0
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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
67 INTSEL
76 GND
63 CDD
79 CDA
65 RXD
77 RXA
66 VCC
64 RID
78 RIA
80 n.c.
62 n.c.
n.c. n.c. DSRA CTSA DTRA VCC RTSA INTA CSA
1 2 3 4 5 6 7 8 9
61 n.c.
75 D7
74 D6
73 D5
72 D4
71 D3
70 D2
69 D1
68 D0
60 n.c. 59 DSRD 58 CTSD 57 DTRD 56 GND 55 RTSD 54 INTD 53 CSD 52 TXD 51 IOR 50 TXC 49 CSC 48 INTC 47 RTSC 46 VCC 45 DTSC 44 CTSC 43 DSRC 42 n.c. 41 n.c.
TXA 10 IOW 11 TXB 12 CSB 13 INTB 14 RTSB 15 GND 16 DTRB 17 CTSB 18 DSRB 19 n.c. 20
SC16C754BIB80
n.c. 21
n.c. 22
CDB 23
RIB 24
RXB 25
CLKSEL 26
n.c. 27
A2 28
A1 29
A0 30
XTAL1 31
XTAL2 32
RESET 33
RXRDY 34
TXRDY 35
GND 36
RXC 37
RIC 38
CDC 39
n.c. 40
002aaa867
Fig 3. Pin configuration for LQFP80
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Product data sheet
Rev. 02 -- 13 June 2005
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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
65 INTSEL
GND
DSRA 10 CTSA 11 DTRA 12 VCC 13 RTSA 14 INTA 15 CSA 16 TXA 17 IOW 18 TXB 19 CSB 20 INTB 21 RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 CDB 27 RIB 28 RXB 29 CLKSEL 30 n.c. 31 A2 32 A1 33 A0 34 XTAL1 35 XTAL2 36 RESET 37 RXRDY 38 TXRDY 39 GND 40 RXC 41 RIC 42 CDC 43
61 CDD 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 INTD 54 CSD 53 TXD 52 IOR 51 TXC 50 CSC 49 INTC 48 RTSC 47 VCC 46 DTRC 45 CTSC 44 DSRC
002aaa868
CDA
63 RXD
RXA
64 VCC
SC16C754BIA68
Fig 4. Pin configuration for PLCC68
5.2 Pin description
Table 2: Symbol A0 A1 A2 CDA CDB CDC CDD CLKSEL Pin description Pin LQFP64 LQFP80 PLCC68 24 23 22 64 18 31 49 30 29 28 79 23 39 63 26 34 33 32 9 27 43 61 30 I I I I I Address 0 select bit. Internal registers address selection. Address 1 select bit. Internal registers address selection. Address 2 select bit. Internal registers address selection. Carrier Detect (active LOW). These inputs are associated with individual UART channels A through D. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Clock Select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset, a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value. This pin is associated with LQFP80 and PLCC68 packages only. This pin is connected to VCC internally on LQFP64 package.
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Type
Description
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Product data sheet
Rev. 02 -- 13 June 2005
62 RID
RIA
D7
D6
D5
D4
D3
68 D2
67 D1
66 D0
9
8
7
6
5
4
3
2
1
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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 2: Symbol CSA CSB CSC CSD CTSA CTSB CTSC CTSD
Pin description ...continued Pin LQFP64 LQFP80 PLCC68 7 11 38 42 2 16 33 47 9 13 49 53 4 18 44 58 16 20 50 54 11 25 45 59 I Clear to Send (active LOW). These inputs are associated with individual UART channels A through D. A logic 0 (LOW) on the CTS pins indicates the modem or data set is ready to accept transmit data from the SC16C754B. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data Set Ready (active LOW). These inputs are associated with individual UART channels A through D. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Data Terminal Ready (active LOW). These outputs are associated with individual UART channels A through D. A logic 0 (LOW) on these pins indicates that the SC16C754B is powered-on and ready. These pins can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Signal and power ground. Interrupt A, B, C, and D (active HIGH). These pins provide individual channel interrupts INTA through INTD. INTA through INTD are enabled when MCR[3] is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space, or when a modem status flag is detected. INTA to INTD are in the high-impedance state after reset. Interrupt select (active HIGH with internal pull-down). INTSEL can be used in conjunction with MCR[3] to enable or disable the 3-state interrupts INTA to INTD or override MCR[3] and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Driving this pin LOW allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the 3-state outputs. This pin is associated with LQFP80 and PLCC68 packages only. This pin is connected to GND internally on the LQFP64 package. Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR will load the contents of an internal register defined by address bits A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external CPU. I Chip Select (active LOW). These pins enable data transfers between the user CPU and the SC16C754B for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic LOW on the respective CSA through CSD pins. Type Description
D0 to D7
53, 54, 55, 56, 57, 58, 59, 60 1 17 32 48 3 15 34 46
68, 69, 70, 71, 72, 73, 74, 75 3 19 43 59 5 17 45 57
66, 67, I/O 68, 1, 2, 3, 4, 5 10 26 44 60 12 24 46 58 O I
DSRA DSRB DSRC DSRD DTRA DTRB DTRC DTRD
GND INTA INTB INTC INTD
14, 28, 45, 61 6 12 37 43
16, 36, 56, 76 8 14 18 54
6, 23, 40, 57 15 21 49 55
I O
INTSEL
-
67
65
I
IOR
40
51
52
I
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 2: Symbol IOW
Pin description ...continued Pin LQFP64 LQFP80 PLCC68 9 11 18 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW will transfer the contents of the data bus (D[7:0]) from the external CPU to an internal register that is defined by address bits A[2:0] and CSA and CSD. not connected Type Description
n.c.
-
1, 2, 20, 31 21, 22, 27, 40, 41, 42, 60, 61, 62, 80 33 37
-
RESET
27
I
Reset. This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. RESET is an active HIGH input. Ring Indicator (active LOW). These inputs are associated with individual UART channels, A through D. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR). Request to Send (active LOW). These outputs are associated with individual UART channels, A through D. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins only affect the transmit and receive operations when Auto-RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the SC16C754B. During the local loop-back mode, these RX input pins are disabled and TX data is connected to the UART RX input internally. Receive Ready (active LOW). RXRDY contains the wire-ORed status of all four receive channel FIFOs, RXRDY A to RXRDY D. It goes LOW when the trigger level has been reached or a time-out interrupt occurs. It goes HIGH when all RX FIFOs are empty and there is an error in RX FIFO. This pin is associated with LQFP80 and PLCC68 packages only. Transmit data. These outputs are associated with individual serial transmit channel data from the SC16C754B. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready (active LOW). TXRDY contains the wire-ORed status of all four transmit channel FIFOs, TXRDY A to TXRDY D. It goes LOW when there are a trigger level number of spaces available. It goes HIGH when all four TX buffers are full. This pin is associated with LQFP80 and PLCC68 packages only.
RIA RIB RIC RID RTSA RTSB RTSC RTSD
63 19 30 50 5 13 36 44
78 24 38 64 7 15 47 55
8 28 42 62 14 22 48 56
I
O
RXA RXB RXC RXD RXRDY
62 20 29 51 -
77 25 37 65 34
7 29 41 63 38
I
O
TXA TXB TXC TXD TXRDY
8 10 39 41 -
10 12 50 52 35
17 19 51 53 39
O
O
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Product data sheet
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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 2: Symbol VCC XTAL1
Pin description ...continued Pin LQFP64 LQFP80 PLCC68 4, 21, 35, 52 25 6, 46, 66 13, 47, 64 31 35 I I Power supply input. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 14). Alternatively, an external clock can be connected to this pin to provide custom data rates. Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output. Type Description
XTAL2
26
32
36
O
6. Functional description
The SC16C754B UART is pin-compatible with the SC16C554 and SC16C654 UARTs. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC16C754B UART can be read at any time during functional operation by the processor. The SC16C754B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The SC16C754B has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 - 1).
6.1 Trigger levels
The SC16C754B provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR.
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2 Hardware flow control
Hardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With Auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the levels at which RTS is activated/deactivated. If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
UART 1 SERIAL TO PARALLEL RX FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL TX FIFO FLOW CONTROL CTS RTS TX RX RTS CTS
UART 2 PARALLEL TO SERIAL TX FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RX FIFO FLOW CONTROL
002aaa228
RX
TX
Fig 5. Autoflow control (Auto-RTS and Auto-CTS) example
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2.1 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 1 "Block diagram of SC16C754B" on page 3). Figure 6 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.
RX
Start
byte N
Stop
Start
byte N + 1
Stop
Start
RTS
IOR
1
2
N
N+1
002aaa226
(1) N = receiver FIFO trigger level. (2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.
Fig 6. RTS functional timing
6.2.2 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.
TX
Start
byte 0 to 7
Stop
Start
byte 0 to 7
Stop
CTS
002aaa227
(1) When CTS is LOW, the transmitter keeps sending serial data out. (2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but it does not send the next byte. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 7. CTS functional timing
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3 Software flow control
Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options.
Table 3: EFR[3] 0 1 0 1 X X X 1 0 1 0 Software flow control options (EFR[3:0]) EFR[2] 0 0 1 1 X X X 0 1 1 0 EFR[1] X X X X 0 1 0 1 1 1 1 EFR[0] X X X X 0 0 1 1 1 1 1 TX, RX software flow controls no transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 no receive flow control receiver compares Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 or Xon2, Xoff1 or Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 or Xon2, Xoff1 or Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 no transmit flow control receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Remark: When using software flow control, the Xon/Xoff characters cannot be used for data characters. There are two other enhanced features relating to software flow control:
* Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.
* Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO.
6.3.1 RX
When software flow control operation is enabled, the SC16C754B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character is received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH. To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears.
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3.2 TX
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2 and Xon1/Xon2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 8 shows an example of software flow control.
6.3.3 Software flow control example
UART1 UART2
TRANSMIT FIFO
RECEIVE FIFO
PARALLEL-TO-SERIAL
data
SERIAL-TO-PARALLEL
Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL
Xon-1 WORD
Xon-1 WORD
Xon-2 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-1 WORD
Xoff-2 WORD
compare programmed Xon-Xoff characters
Xoff-2 WORD
002aaa229
Fig 8. Software flow control example
6.3.3.1
Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.
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Product data sheet
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SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0F to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0D to UART1, informing UART1 to resume transmission.
6.4 Reset
Table 4 summarizes the state of register after reset.
Table 4: Register Interrupt enable register Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register Enhanced feature register Receiver holding register Transmitter holding register Transmission control register Trigger level register Register reset functions Reset control RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (1Dh) all bits cleared bit 5 and bit 6 set; all other bits cleared bits 3:0 cleared; bits 7:4 input signals all bits cleared pointer logic cleared pointer logic cleared all bits cleared all bits cleared
Remark: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET, that is, they hold their initialization values during reset. Table 5 summarizes the state of registers after reset.
Table 5: Signal TX RTS DTR RXRDY TXRDY Signal RESET functions Reset control RESET RESET RESET RESET RESET Reset state HIGH HIGH HIGH HIGH LOW
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6.5 Interrupts
The SC16C754B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.
Table 6: IIR[5:0] 00 0001 00 0110 Interrupt control functions Priority level None 1 Interrupt type none receiver line status Interrupt source none OE, FE, PE, or BI errors occur in characters in the RX FIFO Interrupt reset method none FE, PE, BI: all erroneous characters are read from the RX FIFO. OE: read LSR 00 1100 00 0100 2 2 RX time-out RHR interrupt stale data in RX FIFO DRDY (data ready) (FIFO disable) RX FIFO above trigger level (FIFO enable) 00 0010 3 THR interrupt TFE (THR empty) (FIFO disable) TX FIFO passes above trigger level (FIFO enable) 00 0000 01 0000 10 0000 4 5 6 modem status Xoff interrupt CTS, RTS MSR[3:0] = 0 receive Xoff character(s)/special character read MSR receive Xon character(s)/Read of IIR read IIR or a write to the THR read RHR read RHR
RTS pin or CTS pin change state from read IIR active (LOW) to inactive (HIGH)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros. For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the IIR.
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6.5.1 Interrupt mode operation
In interrupt mode (if any bit of IER[3:0] is `1') the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see if any interrupt needs to be serviced. Figure 9 shows interrupt mode operation.
IOW / IOR INT PROCESSOR
IIR
IER 1 1 1 1
THR
RHR
002aaa230
Fig 9. Interrupt mode operation
6.5.2 Polled mode operation
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 10 shows FIFO polled mode operation.
IOW / IOR PROCESSOR
LSR
IER 0 0 0 0
THR
RHR
002aaa231
Fig 10. FIFO polled mode operation
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6.6 DMA operation
There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time.
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)
Figure 11 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
TX
RX
TXRDY
RXRDY
wrptr
at least one location filled
rdptr
at least one location filled
TXRDY
RXRDY
wrptr
FIFO EMPTY
rdptr
FIFO EMPTY
002aaa232
Fig 11. TXRDY and RXRDY in DMA mode 0/FIFO disable
6.6.1.1
Transmitter When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has been loaded into it.
6.6.1.2
Receiver RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty.
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6.6.2 Block DMA transfers (DMA mode 1)
Figure 12 shows TXRDY and RXRDY in DMA mode 1.
wrptr
TX
trigger level TXRDY rdptr
RX
RXRDY
FIFO full trigger level wrptr TXRDY RXRDY
rdptr
FIFO EMPTY
002aaa869
Fig 12. TXRDY and RXRDY in DMA mode 1
6.6.2.1
Transmitter TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full.
6.6.2.2
Receiver RXRDY becomes active when the trigger level has been reached, or when a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7].
6.7 Sleep mode
Sleep mode is an enhanced feature of the SC16C754B UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
* The serial data input line, RX, is idle (see Section 6.8 "Break and time-out
conditions").
* The TX FIFO and TX shift register are empty. * There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will not be entered if there is data in the RX FIFO. In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO. Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLH.
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6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C754B UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 13. The output frequency of the baud rate generator is 16x the baud rate. The formula for the divisor is: XTAL1 crystal input frequency --------------------------------------------------------------------------- prescaler divisor = -------------------------------------------------------------------------------( desired baud rate x 16 ) Where: prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected) prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected). Remark: The default value of prescaler after reset is divide-by-1. Figure 13 shows the internal prescaler and baud rate generator circuitry.
PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC
MCR[7] = 0 internal baud rate clock for transmitter and receiver
input clock reference clock MCR[7] = 1
BAUD RATE GENERATOR LOGIC
PRESCALER LOGIC (DIVIDE-BY-4)
002aaa233
Fig 13. Prescaler and baud rate generator block diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as no baud clock will be generated. Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz, respectively. Figure 14 shows the crystal clock circuit reference.
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Baud rates using a 1.8432 MHz crystal Divisor used to generate 16x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Baud rates using a 3.072 MHz crystal Divisor used to generate 16x clock 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Percent error difference between desired and actual 2.86 0.69 0.026 0.058 Percent error difference between desired and actual
Table 7:
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8:
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400
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XTAL1
XTAL2
XTAL1
XTAL2
1.5 k
X1 1.8432 MHz
X1 1.8432 MHz
C1 22 pF
C2 33 pF
C1 22 pF
C2 47 pF
002aaa870
Fig 14. Crystal oscillator connection
7. Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9.
Table 9: A2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1
[1] [2] [3] [4] [5] [6]
Register map - read/write properties A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 Read mode receive holding register (RHR) interrupt enable register (IER) interrupt identification register (IIR) line control register (LCR) modem control register (MCR) [1] line status register (LSR) modem status register (MSR) scratchpad register (SPR) divisor latch LSB (DLL) [2] [3] divisor latch MSB (DLH) [2] [3] enhanced feature register (EFR) [2] [4] Xon1 word [2] [4] Xon2 word [2] [4] Xoff1 word [2] [4] Xoff2 word [2] [4] transmission control register (TCR) [2] [5] trigger level register (TLR) [2] [5] FIFO ready register [2] [6] Write mode transmit holding register (THR) interrupt enable register FIFO control register (FCR) line control register modem control register [1] n/a n/a scratchpad register divisor latch LSB [2] [3] divisor latch MSB [2] [3] enhanced feature register [2] [4] Xon1 word [2] [4] Xon2 word [2] [4] Xoff1 word [2] [4] Xoff2 word [2] [4] transmission control register [2] [5] trigger level register [2] [5]
A1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1
MCR[7] can only be modified when EFR[4] is set. Accessed by a combination of address pins and register bits. Accessible only when LCR[7] is logic 1. Accessible only when LCR is set to 1011 1111 (xBF). Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables. Accessible only when CSA - CSD = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).
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Table 10 lists and describes the SC16C754B internal registers.
Table 10: SC16C754B internal registers Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/ Write R W
A2 A1 A0 Register Bit 7 General Register set [1] 0 0 0 0 0 0 0 0 1 RHR THR IER bit 7 bit 7 0/CTS interrupt enable [2] RX trigger level (MSB) FCR[0]
bit 6 bit 6 0/RTS interrupt enable [2]
bit 5 bit 5 0/Xoff [2]
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1 THR empty interrupt
bit 0 bit 0
0/X Sleep modem receive mode [2] status line status interrupt interrupt 0/TX trigger level (LSB) [2] 0/Xoff DMA mode select TX FIFO reset
Rx data R/W available interrupt W
0
1
0
FCR
RX trigger 0/TX level (LSB) trigger level (MSB) [2] FCR[0] 0/CTS, RTS
RX FIFO FIFO reset enable
0
1
0
IIR
interrupt interrupt priority priority bit 2 bit 1 number of stop bits FIFO ready enable
interrupt priority bit 0 word length bit 1 RTS
interrupt R status word length bit 0 DTR R/W
0
1
1
LCR
DLAB
break control bit TCR and TLR enable [2]
set parity parity type parity select enable 0/Xon Any [2] 0/enable IRQ loop-back enable OP break interrupt CTS bit 4 bit 4 bit 4 RX FIFO A status bit 4 bit 12 framing error CD bit 3 bit 3 bit 3
1
0
0
MCR
1x or 1x/4 clock [2] 0/error in RX FIFO CD bit 7 bit 7 bit 7 RX FIFO D status bit 7 bit 15 set [4]
R/W
1 1 1 1 1 1
0 1 1 1 1 1
1 0 1 0 1 1
LSR MSR SPR TCR TLR FIFO Rdy DLL DLH EFR
THR and THR TSR empty empty RI bit 6 bit 6 bit 6 RX FIFO C status bit 6 bit 14 DSR bit 5 bit 5 bit 5 RX FIFO B status bit 5 bit 13
parity error overrun error RI bit 2 bit 2 bit 2 DSR bit 1 bit 1 bit 1
data in receiver CTS bit 0 bit 0 bit 0
R R R/W R/W R/W
TX FIFO TX FIFO D status C status bit 3 bit 11 bit 2 bit 10
TX FIFO TX FIFO R B status A status bit 1 bit 9 software flow control bit 1 bit 1 bit 1 bit 1 bit 1 bit 0 bit 8 R/W R/W
Special Register set [3] 0 0 0 0 0 1 0 1 0
Enhanced Register
Auto CTS Auto RTS
Special Enable software software flow character enhanced flow control detect functions control [2] bit 2 bit 3 bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 bit 3 bit 3 bit 3 bit 3 bit 2 bit 2 bit 2 bit 2
software R/W flow control bit 0 bit 0 bit 0 bit 0 bit 0 R/W R/W R/W R/W
1 1 1 1
[1] [2] [3] [4]
0 0 1 1
0 1 0 1
Xon1 Xon2 Xoff1 Xoff2
bit 7 bit 7 bit 7 bit 7
bit 6 bit 6 bit 6 bit 6
These registers are accessible only when LCR[7] = 0. This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled. The Special Register set is accessible only when LCR[7] is set to a logic 1. Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to `BFh'.
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Remark: Refer to the notes under Table 9 for more register access information.
7.1 Receiver Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled, location zero of the FIFO is used to store the characters. Remark: In this case, characters are overwritten if overflow occurs. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character.
7.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs.
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7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11 shows FIFO control register bit settings.
Table 11: Bit 7:6 FIFO Control Register bits description Description
Symbol
FCR[7] (MSB), RCVR trigger. Sets the trigger level for the RX FIFO. FCR[6] (LSB) 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters
5:4
FCR[5] (MSB), TX trigger. Sets the trigger level for the TX FIFO. FCR[4] (LSB) 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces FCR[5:4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function.
3
FCR[3]
DMA mode select. logic 0 = Set DMA mode `0' logic 1 = Set DMA mode `1'
2
FCR[2]
Reset TX FIFO. logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
Reset RX FIFO. logic 0 = no FIFO receive reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO
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7.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the line control register bit settings.
Table 12: Bit 7 Line Control Register bits description Description Divisor latch enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Break control bit. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition) logic 1 = forces the transmitter output (TX) to a logic 0 to alert the communication terminal to a line break condition 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1). logic 0 = parity is not forced (normal default condition) LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data 4 LCR[4] Parity type select. logic 0 = odd parity is generated (if LCR[3] = 1) logic 1 = even parity is generated (if LCR[3] = 1) 3 LCR[3] Parity enable. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during transmission and the receiver checks for received parity 2 LCR[2] Number of stop bits. Specifies the number of stop bits. 0 = 1 stop bit (word length = 5, 6, 7, 8) 1 = 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received. 00 - 5 bits 01 - 6 bits 10 - 7 bits 11 - 8 bits
Symbol LCR[7]
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7.5 Line Status Register (LSR)
Table 13 shows the line status register bit settings.
Table 13: Bit 7 Line Status Register bits description Description FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. logic 0 = Transmit Hold Register is not empty logic 1 = Transmit Hold Register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled. 4 LSR[4] Break interrupt. logic 0 = no break condition (normal default condition) logic 1 = a break condition occurred and associated byte is 00, that is, RX was LOW for one character time frame 3 LSR[3] Framing error. logic 0 = no framing error in data being read from RX FIFO (normal default condition) logic 1 = framing error occurred in data being read from RX FIFO, that is, received data did not have a valid stop bit 2 LSR[2] Parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from RX FIFO 1 LSR[1] Overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 LSR[0] Data in receiver. logic 0 = no data in receive FIFO (normal default condition) logic 1 = at least one character in the RX FIFO
Symbol LSR[7]
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RHR.
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7.6 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 14 shows Modem Control Register bit settings.
Table 14: Bit 7 Modem Control Register bits description Symbol MCR[7]
[1]
Description Clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input
6
MCR[6]
[1]
TCR and TLR enable. logic 0 = no action logic 1 = enable access to the TCR and TLR registers
5
MCR[5]
[1]
Xon Any. logic 0 = disable Xon Any function logic 1 = enable Xon Any function
4
MCR[4]
Enable loop-back. logic 0 = normal operating mode Logic 1 = enable local loop-back mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4] and the TX output is looped back to the RX input internally.
3
MCR[3]
IRQ enable OP. logic 0 = forces INTA-INTB outputs to the 3-state mode and OP output to HIGH state logic 1 = forces the INTA-INTB outputs to the active state and OP output to LOW state. In loop-back mode, controls MSR[7].
2
MCR[2]
FIFO Ready enable. logic 0 = disable the FIFO Rdy register logic 1 = enable the FIFO Rdy register. In loop-back mode, controls MSR[6].
1
MCR[1]
RTS logic 0 = force RTS output to inactive (HIGH) logic 1 = force RTS output to active (LOW). In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled by hardware flow control.
0
MCR[0]
DTR logic 0 = force DTR output to inactive (HIGH) logic 1 = force DTR output to active (LOW). In loop-back mode, controls MSR[5].
[1]
MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
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7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows Modem Status Register bit settings per channel.
Table 15: Bit 7 Modem Status Register bits description Description CD (active HIGH, logical 1). This bit is the complement of the CD input during normal mode. During internal loop-back mode, it is equivalent to MCR[3]. RI (active HIGH, logical 1). This bit is the complement of the RI input during normal mode. During internal loop-back mode, it is equivalent to MCR[2]. DSR (active HIGH, logical 1). This bit is the complement of the DSR input during normal mode. During internal loop-back mode, it is equivalent MCR[0]. CTS (active HIGH, logical 1). This bit is the complement of the CTS input during normal mode. During internal loop-back mode, it is equivalent to MCR[1]. CD. Indicates that CD input (or MCR[3] in loop-back mode) has changed state. Cleared on a read. RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed state from LOW to HIGH. Cleared on a read. DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has changed state. Cleared on a read. CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has changed state. Cleared on a read.
Symbol MSR[7] [1]
6 5
MSR[6] [1] MSR[5] [1]
4
MSR[4] [1]
3 2 1 0
[1]
MSR[3] MSR[2] MSR[1] MSR[0]
The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and MCR (in loop-back) registers are active HIGH.
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7.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output signal is activated in response to interrupt generation. Table 16 shows Interrupt Enable Register bit settings.
Table 16: Bit 7 Interrupt Enable Register bits description Description CTS interrupt enable. logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt 6 IER[6]
[1] [1]
Symbol IER[7]
RTS interrupt enable. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt
5
IER[5]
[1]
Xoff interrupt. logic 0 = disable the Xoff interrupt (normal default condition) logic 1 = enable the Xoff interrupt
4
IER[4]
[1]
Sleep mode. logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode. See Section 6.7 "Sleep mode" for details.
3
IER[3]
Modem Status Interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt
2
IER[2]
Receive Line Status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt
1
IER[1]
Transmit Holding Register interrupt. logic 0 = disable the THR interrupt (normal default condition) logic 1 = enable the THR interrupt
0
IER[0]
Receive Holding Register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt
[1]
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will cause a new interrupt if the THR is below the threshold.
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7.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows Interrupt Identification Register bit settings.
Table 17: Bit 7-6 5 4 3-1 0 Interrupt Identification Register bits description Description Mirror the contents of FCR[0]. RTS/CTS LOW-to-HIGH change of state. 1 = Xoff/Special character has been detected. 3-bit encoded interrupt. See Table 18. Interrupt status. logic 0 = an interrupt is pending logic 1 = no interrupt is pending
Symbol IIR[7:6] IIR[5] IIR[4] IIR[3:1] IIR[0]
The interrupt priority list is shown in Table 18.
Table 18: Interrupt priority list IIR[4] 0 0 0 0 0 1 0 IIR[3] 0 1 0 0 0 0 0 IIR[2] 1 1 1 0 0 0 0 IIR[1] 1 0 0 1 0 0 0 IIR[0] 0 0 0 0 0 0 0 Source of the interrupt Receiver Line Status error Receiver time-out interrupt RHR interrupt THR interrupt Modem interrupt Received Xoff signal/ special character CTS, RTS change of state from active (LOW) to inactive (HIGH)
Priority IIR[5] level 1 2 2 3 4 5 6 0 0 0 0 0 0 1
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7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the Enhanced Feature Register bit settings.
Table 19: Bit 7 Enhanced Feature Register bits description Description CTS flow control enable. logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTS pin. 6 EFR[6] RTS flow control enable. logic 0 = RTS flow control is disabled (normal default condition) logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached. 5 EFR[5] Special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. Received data is compared with Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special character has been detected. 4 EFR[4] Enhanced functions enable bit. logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]. logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a write enable. 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 "Software flow control options (EFR[3:0])".
Symbol EFR[7]
7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Note that DLL and DLH can only be written to before Sleep mode is enabled, that is, before IER[4] is set.
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7.12 Transmission Control Register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 20 shows Transmission Control Register bit settings.
Table 20: Bit 7:4 3:0 Transmission Control Register bits description Description RX FIFO trigger level to resume transmission (0-60). RX FIFO trigger level to halt transmission (0-60).
Symbol TCR[7:4] TCR[3:0]
TCR trigger levels are available from 0 to 60 bytes with a granularity of four. Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious operation of the device.
7.13 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 21 shows Trigger Level Register bit settings.
Table 21: Bit 7:4 3:0 Trigger Level Register bits description Description RX FIFO trigger levels (4 to 60), number of characters available. TX FIFO trigger levels (4 to 60), number of spaces available.
Symbol TLR[7:4] TLR[3:0]
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 to 60 bytes are available with a granularity of four. The TLR should be programmed for N4, where N is the desired trigger level.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels.
Table 22: Bit 7:4 FIFO ready register bits description Description 0 = there are less than a RX trigger level number of characters in the RX FIFO 1 = the RX FIFO has more than a RX trigger level number of characters available for reading or a time-out condition has occurred 3:0 FIFO Rdy[3:0] 0 = there are less than a TX trigger level number of spaces available in the TX FIFO 1 = there are at least a TX trigger level number of spaces available in the TX FIFO
Symbol FIFO Rdy[7:4]
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The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back is disabled. The address is 111.
8. Programmer's guide
The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access. Some streamlining through interleaving can be obtained when programming all the registers.
Table 23: Command set baud rate to VALUE1, VALUE2 Register programming guide Actions read LCR (03), save in temp set LCR (03) to 80 set DLL (00) to VALUE1 set DLM (01) to VALUE2 set LCR (03) to temp set Xoff1, Xon1 to VALUE1, VALUE2 read LCR (03), save in temp set LCR (03) to BF set Xoff1 (06) to VALUE1 set Xon1 (04) to VALUE2 set LCR (03) to temp set Xoff2, Xon2 to VALUE1, VALUE2 read LCR (03), save in temp set LCR (03) to BF set Xoff-2 (07) to VALUE1 set Xon-2 (05) to VALUE2 set LCR (03) to temp set software flow control mode to VALUE read LCR (03), save in temp set LCR (03) to BF set EFR (02) to VALUE set LCR (03) to temp set flow control threshold to VALUE read LCR (03), save in temp1 set LCR (03) to BF read EFR (02), save in temp2 set EFR (02) to 10 + temp2 set LCR (03) to 00 read MCR (04), save in temp3 set MCR (04) to 40 + temp3 set TCR (06) to VALUE set MCR (04) to temp3 set LCR (03) to BF set EFR (02) to temp2 set LCR (03) to temp1
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Register programming guide ...continued Actions read LCR (03), save in temp1 set LCR (03) to BF read EFR (02), save in temp2 set EFR (02) to 10 + temp2 set LCR (03) to 00 read MCR (04), save in temp3 set MCR (04) to 40 + temp3 set TLR (07) to VALUE set MCR (04) to temp3 set LCR (03) to BF set EFR (02) to temp2 set LCR (03) to temp1
Table 23: Command
set TX FIFO and RX FIFO thresholds to VALUE
read FIFO Rdy register
read MCR (04), save in temp1 set temp2 = temp1 x EF
[1]
set MCR (04) = 40 + temp2 read FFR (07), save in temp2 pass temp2 back to host set MCR (04) to temp1 set prescaler value to divide-by-1 read LCR (03), save in temp1 set LCR (03) to BF read EFR (02), save in temp2 set EFR (02) to 10 + temp2 set LCR (03) to 00 read MCR (04), save in temp3 set MCR (04) to temp3 x 7F set LCR (03) to BF set EFR (02) to temp2 set LCR (03) to temp1 set prescaler value to divide-by-4 read LCR (03), save in temp1 ret LCR (03) to BF read EFR (02), save in temp2 set EFR (02) to 10 + temp2 set LCR (03) to 00 read MCR (04), save in temp3 set MCR (04) to temp3 + 80 set LCR (03) to BF set EFR (02) to temp2 set LCR (03) to temp1
[1] x sign here means bit-AND.
[1]
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9. Limiting values
Table 24: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO Tamb Tstg Parameter supply voltage input voltage output voltage ambient temperature storage temperature operating in free-air Conditions Min -0.3 -0.3 -40 -65 Max 7 VCC + 0.3 VCC + 0.3 +85 +150 Unit V V V C C
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10. Static characteristics
Table 25: Static characteristics Tolerance of VCC 10 %, unless otherwise specified. Symbol Parameter VCC VI VIH VIL VO VOH supply voltage input voltage HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output voltage IOH = -8 mA IOH = -4 mA IOH = -800 A IOH = -400 A VOL LOW-level output IOL = 8 mA voltage [5] IOL = 4 mA IOL = 2 mA IOL = 1.6 mA Ci Tamb Tj f(i)XTAL1 ICC ICCsleep
[1] [2] [3] [4] [5] [6] [7] [8]
[1]
Conditions Min
VCC = 2.5 V Typ VCC +25 25 50 200 Max VCC VCC 0.65 VCC 0.4 0.4 18 +85 125 50 4.5 VCC - 10 % 0 1.6 0 1.85 1.85 -40
[6]
VCC = 3.3 V and 5 V Min 0 2.0 0 2.0 2.0 -40 0 Typ VCC +25 25 50 200 Max
Unit
VCC + 10 % VCC - 10 %
VCC + 10 % V VCC VCC 0.8 VCC 0.4 0.4 18 +85 125 80 6 V V V V V V V V V V V V pF C C MHz % mA A
[1]
[2] [3] [4] [3] [4] [3] [4] [3] [4]
input capacitance ambient temperature junction temperature crystal input frequency clock duty cycle supply current sleep current f = 5 MHz
[8] [9]
operating in free air
0 -
[7]
Meets TTL levels, VIO(min) = 2 V and VIH(max) = 0.8 V on non-hysteresis inputs. Applies for external output buffers. These parameters apply for D7 to D0. These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. Except XTAL2, VOL = 1 V typical. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 C. The customer is responsible for verifying junction temperature. Applies to external clock; crystal oscillator max. 24 MHz. Measurement condition, normal operation other than Sleep mode: VCC = 3.3 V; Tamb = 25 C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of 1. When using crystal oscillator. The use of an external clock will increase the sleep current.
[9]
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11. Dynamic characteristics
Table 26: Dynamic characteristics Tamb = -40 C to +85 C; tolerance of VCC 10 %, unless otherwise specified. Symbol Parameter t1w, t2w fXTAL t6s t6h t7d t7w t7h t9d t12d t12h t13d t13w t13h t15d t16s t16h t17d t18d t19d t20d t21d t22d t23d t24d t25d t26d t27d t28d tRESET N
[1]
Conditions 10
[1] [2]
VCC = 2.5 V Min Max 48 90 15 100 100 100 1TRCLK
[3]
VCC = 3.3 V Min 6 0 0 10 26 0 20 10 20 0 25 15 5 [3]
VCC = 5.0 V Min 6 0 0 10 23 0 20 10 15 0 20 15 5 [3]
Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Max 80 26 15 33 24 24 1TRCLK
[3]
Max 80 23 15 29 23 23 1TRCLK
[3]
clock pulse duration oscillator/clock frequency address setup time address hold time IOR delay from chip select IOR strobe width chip select hold time from IOR read cycle delay delay from IOR to data data disable time IOW delay from chip select IOW strobe width chip select hold time from IOW write cycle delay data setup time data hold time delay from IOW to output delay to set interrupt from Modem input delay to reset interrupt from IOR delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY delay from start to reset TXRDY RESET pulse width baud rate divisor 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load
0 0 10 90 0 20 10 20 0 25 20 15 [3]
100 100
[3]
29 45
[3]
28 40
[3]
8TRCLK 24TRCLK 8TRCLK 24TRCLK 8TRCLK 24TRCLK ns 200 1 100 1TRCLK
[3]
200
45 1TRCLK
[3]
200
40 1TRCLK
[3]
ns ns ns ns ns ns
100 100 8TRCLK
[3]
45 45 8TRCLK
[3]
40 40 8TRCLK
[3]
-
-
(216 - 1)
(216 - 1) 1
(216 - 1) 1
Applies to external clock, crystal oscillator max 24 MHz.
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[2] [3]
Maximum frequency = ------RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
1 t 3w
11.1 Timing diagrams
t6h valid address t6s t13h
A0 to A2
CSx t13d
active t15d
t13w active t16s t16h
IOW
D0 to D7
data
002aaa109
Fig 15. General write timing
t6h valid address t6s t7h
A0 to A2
CSx t7d
active t9d
t7w active t12d t12h
IOR
D0 to D7
data
002aaa110
Fig 16. General read timing
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IOW
active t17d
RTS DTR
change of state
change of state
CD CTS DSR t18d
change of state t18d
change of state
INT
active t19d
active
active
IOR
active
active t18d
active
RI
change of state
002aaa352
Fig 17. Modem input/output timing
t2w EXTERNAL CLOCK t3w
t1w
002aaa112
1 f XTAL = ------t 3w Fig 18. External clock timing
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
next data start bit
RX
5 data bits 6 data bits 7 data bits INT t20d active t21d active
IOR
16 baud rate clock
002aaa113
Fig 19. Receive timing
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
next data start bit
RX
t25d RXRDY active data ready t26d IOR active
002aab063
Fig 20. Receive ready timing in non-FIFO mode
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
RX
first byte that reaches the trigger level
t25d RXRDY active data ready t26d IOR active
002aab064
Fig 21. Receive ready timing in FIFO mode
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
next data start bit
TX
5 data bits 6 data bits 7 data bits INT t22d t23d IOW active active transmitter ready t24d active
16 baud rate clock
002aaa116
Fig 22. Transmit timing
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
next data start bit
TX
IOW
active t28d
D0 to D7
byte #1
t27d TXRDY active transmitter ready
002aab062
transmitter not ready
Fig 23. Transmit ready timing in non-FIFO mode
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
TX
5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #32 t27d
TXRDY
FIFO full
002aab065
Fig 24. Transmit ready timing in FIFO mode (DMA mode `1')
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12. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1
c
y X
48 49
33 32 ZE
A
e E HE wM pin 1 index bp L 64 1 ZD bp D HD wM B vM B 16 17 detail X Lp A A2 A1 (A 3)
e
vM A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.23 0.13 c 0.20 0.09 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.4 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 0.64 0.36 0.64 0.36 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT414-1 REFERENCES IEC 136E06 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-20
Fig 25. Package outline SOT414-1 (LQFP64)
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LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 26. Package outline SOT315-1 (LQFP80)
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PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3) Lp detail X
k
9
27
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e A3 eD eE HD bp b1 max. min.
mm inches 4.57 4.19 0.51 0.25 0.01 3.3 0.13 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
23.62 23.62 25.27 25.27 1.22 24.33 24.33 1.27 22.61 22.61 25.02 25.02 1.07 24.13 24.13 0.93 0.89 0.93 0.89
45 o
0.180 0.02 0.165
0.021 0.032 0.958 0.958 0.05 0.013 0.026 0.950 0.950
0.995 0.995 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.985 0.985 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-14
Fig 27. Package outline SOT188-2 (PLCC68)
9397 750 14668 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 13 June 2005
45 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14668 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 13 June 2005
46 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
13.5 Package related soldering information
Table 27: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
9397 750 14668
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 13 June 2005
47 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
14. Revision history
Table 28: Revision history Release date 20050613 Data sheet status Product data sheet Change notice Doc. number 9397 750 14668 Supersedes SC16C754B_1 Document ID SC16C754B_2 Modifications:
* * * * *
Section 1 "General description", 3rd paragraph: added `LQFP64' Section 2 "Features", 4th bullet: changed `baud rate' to `data rate' (2 places) Table 1 "Ordering information": added LQFP64 package offering Figure 2 "Pin configuration for LQFP64" added Table 2 "Pin description": - added column for LQFP64 pinning - descriptions for CLKSEL, INTSEL, RXRDY, TXRDY modified to indicate the package-type to which they apply
* * *
Table 10 "SC16C754B internal registers": shading removed, replaced with reference to Table note 2 Table 24 "Limiting values": table note removed (statement shown in Section 17 "Disclaimers") Table 25 "Static characteristics": - description following title changed from `VCC = 2.5 V, 3.3 V 10 % or 5 V 10 %' to `Tolerance of VCC 10 %; unless otherwise specified.' - Added `VCC =' to value limits column headings - Table note 5: changed `x2' to `XTAL2'
*
Table 26 "Dynamic characteristics": - symbol `t3w' changed to `fXTAL'; added reference to (new) Table note 2 - under values for t20d, t23d, t25d, t28d: changed `RCLK cycles' to `TRCLK'; added reference to Table note 3; added unit `ns' - symbol N: removed `RCLK cycle(s)' from values (N is a number) - added (new) Table note 2
* *
SC16C754B_1
Figure 25 "Package outline SOT414-1 (LQFP64)" added Section 18 "Trademarks" added Product data sheet 9397 750 13114 -
20050127
9397 750 14668
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 13 June 2005
48 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14668
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 13 June 2005
49 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
20. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 9 Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware flow control . . . . . . . . . . . . . . . . . . . 10 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Software flow control . . . . . . . . . . . . . . . . . . . 12 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Software flow control example . . . . . . . . . . . . 13 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt mode operation . . . . . . . . . . . . . . . . 16 Polled mode operation . . . . . . . . . . . . . . . . . . 16 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 17 Single DMA transfers (DMA mode 0/FIFO disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block DMA transfers (DMA mode 1). . . . . . . . 18 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Break and time-out conditions . . . . . . . . . . . . 19 Programmable baud rate generator . . . . . . . . 19 Register descriptions . . . . . . . . . . . . . . . . . . . 21 Receiver Holding Register (RHR). . . . . . . . . . 23 Transmit Holding Register (THR) . . . . . . . . . . 23 FIFO Control Register (FCR) . . . . . . . . . . . . . 24 Line Control Register (LCR) . . . . . . . . . . . . . . 25 Line Status Register (LSR) . . . . . . . . . . . . . . . 26 Modem Control Register (MCR) . . . . . . . . . . . 27 Modem Status Register (MSR). . . . . . . . . . . . 28 Interrupt Enable Register (IER) . . . . . . . . . . . 29 Interrupt Identification Register (IIR). . . . . . . . 30 Enhanced Feature Register (EFR) . . . . . . . . . 31 Divisor latches (DLL, DLH) . . . . . . . . . . . . . . . 31 Transmission Control Register (TCR) . . . . . . . 32 Trigger Level Register (TLR). . . . . . . . . . . . . . 32 FIFO ready register. . . . . . . . . . . . . . . . . . . . . 32 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 19 Programmer's guide . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 33 35 36 37 38 43 46 46 46 46 47 47 48 49 49 49 49 49
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 June 2005 Document number: 9397 750 14668
Published in The Netherlands

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